The annual International Solid State Conference always reveals the first details about the next generation of NAND flash memory. Intel and SK Hynix are promising memory chips that are said to have area densities in excess of 20Gb/mm² for the first time. The technical implementation is very different.
Higher areal density than Intel PLC NAND (5-bit).
high Media reports Intel introduced a PLC (Penta Level Cell) memory with 5 bits per memory cell at ISSCC 2023, which provides 1.67 TB of storage on an area of 73.3 mm². As far as the editors are aware, this results in the highest NAND flash area density to date of 23.3 Gb/mm².
As before, Intel relies on a floating gate architecture and now stacks 192 cell layers (layers) on top of each other. Although the group simultaneously sold its flash and SSD division to SK Hynix, from which Solidigm emerged, which in turn presented the first SSD with PLC-NAND, it seems that research in this sector is also continuing at Intel.
SK Hynix wants to break 20Gb/mm² with 300 layers of TLC
SK Hynix also wants to break the 20Gb/mm² mark. Instead of packing more bits into cells, SK Hynix continues to rely on 3-bit (TLC) in combination with significantly more layers of cells. The upcoming TLC-NAND should have more than 300 layers and thus offer more than 20 Gb/mm². Storage stays at 1TB, which means a much smaller chip.
In terms of performance too, there should be a significant increase. It cited a read response time of just 34MB and a chip-wide write throughput of 194MB/s. On the other hand, the soon-to-be mass-produced 238-layer NAND from SK Hynix achieves 45 microseconds and 164MB/s. Samsung’s V7, the former flagship in typing, will take a beating.
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